1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a contact structure, a semiconductor device employing the same, and methods of fabricating the contact structure and semiconductor device.
2. Description of Related Art
Discrete devices, such as MOS transistors, are widely used as switching devices in semiconductor devices. With the continued increase in integration density of semiconductor devices, the MOS transistor continues to be reduced in size. In general, when the MOS transistor is reduced in size, the channel resistance of the MOS transistor decreases so that the MOS transistor permits a high driving current and operates at a high switching rate. However, a reduction in the size of the MOS transistor causes not only the foregoing advantages but also some disadvantages.
In general, a reduction in the size of the MOS transistor leads to a decrease in the channel resistance of the MOS transistor, thus improving the switching rate of the MOS transistor. However, the reduction in the size of the MOS transistor can also result in an increase in the electrical resistance of a region (e.g., a conductive line and a contact region) that provides an electrical contact to the vicinity of the MOS transistor. Typically, as the size of the MOS transistor decreases, a channel length thereof also decreases. As a result, capacitance between a gate electrode and a channel of the MOS transistor can be further reduced, and the channel resistance of a channel region can be further lowered, and thus the MOS transistor can be improved in performance. However, a reduction in the channel length of the MOS transistor also leads to a decrease in the area of a contact region that forms an electrical contact with source/drain regions of the MOS transistor. Also, the reduction in the channel length of the MOS transistor can lead to an increased likelihood of the occurrence of the short channel effect. In order to prevent the occurrence of the short channel effect, it is necessary to reduce the junction depth of the source/drain regions of the MOS transistor.
FIGS. 1A and 1B are cross-sectional views illustrating a conventional method of fabricating a semiconductor device having a silicide layer. In FIGS. 1A and 1B, reference character A denotes a first transistor region, and reference character B denotes a second transistor region.
Referring to FIG. 1A, a semiconductor substrate 1 having an isolation layer 3 is prepared to define active regions. A first transistor having a first channel length is formed in the first transistor region A of the semiconductor substrate 1, and a second transistor having a second channel length is formed in the second transistor region B of the semiconductor substrate 1. Here, the second channel length is shorter than the first channel length. The first transistor may include a first gate pattern 11a and first source/drain regions 17a. The first gate pattern 11a may include a first gate dielectric layer 5a, a first gate electrode 7a, and a first hard mask layer 9a, which are sequentially stacked. Also, the first source/drain regions 17a may be formed in the semiconductor substrate 1 on both sides of the first gate pattern 11a. The second transistor may include a second gate pattern 11b and second source/drain regions 17b. The second gate pattern 11b may include a second gate dielectric layer 5b, a second gate electrode 7b, and a second hard mask layer 9b, which are sequentially stacked. Also, the second source/drain regions 17b may be formed in the semiconductor substrate 1 on both sides of the second gate pattern 11b. 
A first gate spacer 15a is formed to cover a sidewall of the first gate pattern 11a, and a second gate spacer 15b is formed to cover a sidewall of the second gate pattern 11b. Thereafter, an insulating layer 19 is formed on the substrate having the first and second transistors and then patterned, thereby forming a first contact hole 19a and a second contact hole 19b. Thus, the first contact hole 19a exposes a first source/drain contact region of the first source/drain region 17a, and the second contact hole 19b exposes a second source/drain contact region of the second source/drain region 17b. The second transistor has a second channel length that is shorter than the first channel length of the first transistor. The second contact hole 19b may be formed using a conventional self-align contact technique.
Referring to FIG. 1B, a first silicide layer 21a having a first thickness is formed on a surface of the first source/drain contact region that is exposed by the first contact hole 19a, and simultaneously, a second silicide layer 21b having a second thickness is formed on a surface of the second source/drain region that is exposed by the second contact hole 19b. Here, the second thickness is equal to the first thickness. As a result, the first silicide layer 21a is formed in the first source/drain contact region that is spaced a predetermined distance apart from the first gate electrode 7a of the first transistor, and the second silicide layer 21b is formed in the second source/drain contact region contacting the second gate spacer 15b. 
In order to lower the contact resistance of the first transistor, the first silicide layer 21a should not be less than a certain thickness. However, when the first silicide layer 21a has a large thickness to lower the contact resistance of the first transistor, the second silicide layer 21b that is formed during the formation of the first silicide layer 21a also has a large thickness. Since the second source/drain contact region of the second transistor is in contact with a sidewall of the second gate spacer 15b, as the thickness of the second silicide layer 21b increases, a ratio of the thickness of the second silicide layer 21b to the junction depth of the second source/drain region also increases. Further, a junction portion E between the second source/drain region and a channel region may come into contact with the second silicide layer 21b. Thus, a short circuit may occur between the second silicide layer 21b and a channel of the second transistor. As a result, the junction portion E may be defective.